1. Technical Field
The present invention relates to a semiconductor device and an electro-optical device that uses a polycrystalline silicon film disposed over a substrate as an active layer of a thin film transistor.
2. Related Art
A thin film transistor is used as a transistor for controlling an electric current that flows into an organic electro-luminescence element of an organic electro-luminescence device. Another example of applications of a thin film transistor is a constituent element of a liquid crystal device that has analog circuits, a typical example of which is an operational amplifier, though not limited thereto, formed on the same single built-in circuit board thereof. In these non-limiting exemplary applications of a thin film transistor, the saturation characteristics of the thin film transistor are utilized in comparison with the counterpart of a MOS transistor that is formed on a silicon substrate, it is known that the saturation characteristics of a thin film transistor are relatively incomplete. Specifically, the saturation characteristics of the thin film transistor show some phenomena that indicate that a drain current increases when a drain voltage level changes. With reference to FIG. 14, these phenomena are explained below.
First Phenomenon: As illustrated in FIG. 14, due to a phenomenon called as “kink effects”, the electric current of a thin film transistor has a tendency to increase at an area where the level of a drain voltage is high. That is, due to the kink effects, the rate of change in the level of a drain current relative to the level of a drain voltage tends to be large thereat. The reason why such a phenomenon occurs is considered as follows. When the level of a drain voltage is raised in the operation of a thin film transistor, a comparatively large electric field concentrates on a drain end once after the level of the drain voltage exceeds a pinch off voltage point. When the intensity of such an electric field exceeds a certain level, electrons that are accelerated by the electric field cause impact ionization so as to form a pair of an electron and a hole. In the case of a bulk type MOS transistor, since the electron hole formed as above flows toward a semiconductor substrate that serves as a bulk, it does not cause so much adverse effects on a source-drain current. In contrast, in the case of a thin film transistor, since a contact is not formed against the electron hole of a channel region, the electron hole enters the channel region to lower a potential of the channel regions As a result thereof, an electron/electronic current increases. In order to relax the concentration of an electric field at a drain end, an LDD (Lightly Doped Drain) structure, which has a lightly doped region opposed to the end portion of a gate electrode in a semiconductor layer, is frequently adopted. However, the LDD structure alone is not sufficient for completely suppressing the kink phenomenon.
Second Phenomenon: When an enhancement type transistor element is used, a pinch off voltage point Vp of a bulk type MOS transistor is defined as an operating point of a drain voltage that is smaller than a point of Vds=Vgs by an amount of Vth. Accordingly, a voltage range of a source-drain voltage Vds that is larger than the pinch off voltage point Vp constitutes a saturation region (i.e., range). In contrast a pinch off voltage point Vp of a thin film transistor is not clearly determined as illustrated in FIG. 14. Therefore, in a thin film transistor, the boundary between a linear region and the saturation region thereof spans a comparatively wide switchover voltage width therebetween. The reason for the above is considered that, according to the configuration of a thin film transistor, the potential of the channel region of the thin film transistor is determined by a relative relationship among a gate voltage, a drain voltage, and a source voltage thereof. That is, it is considered that the drain voltage has effects not only through the semiconductor layer that is the route of an electric current but also through an insulating material that is positioned at an opposite side with respect to a gate electrode. When the LDD structure is adopted as a technical solution to the first phenomenon, since the LDD region constantly provides a parasitic resistance, an effectual drain voltage that is applied to the channel region is relatively small. This is another reason for the above.
Third Phenomenon: A range between the region where a source-drain current increases, which is pointed out as the first phenomenon described above, and the pinch off voltage point, which is pointed out as the second phenomenon described above, constitutes the saturation region of a thin film transistor. However, in the case of a thin film transistor, as understood from FIG. 14, even in the saturation region thereof, the rate of change in the level of a drain current relative to the level of a drain voltage is not satisfactorily small. Thus, it is difficult to expect constant current operation.
In order to address the above-identified problematic phenomena, it is conceivable to adopt the following configurations.
Configuration A: The third problematic phenomenon will be solved if the channel length of the thin film transistor is lengthened. As another advantage, since the intensity of an electric field in the drain direction is reduced when the channel length is increased, the first problematic phenomenon is also partly solved. However, tile channel length must be made considerably large in order to achieve satisfactory characteristics thereof. Disadvantageously, since the gate capacitance increases as the channel length is increased, the high frequency characteristics of the circuit operations thereof are degraded. As another disadvantage thereof, sensitivity for increasing a current by changing a gate voltage is also degraded. As still another disadvantage thereof its scope and field of application is limited because the area occupancy of the thin film transistor increases.
Configuration B: It is known in the related art to form an LDD region at a drain end for the purpose of relaxing the intensity of an electric field at the drain end. It is possible to partly solve the first problematic phenomenon by setting the impurity dope concentration of the LDD region at a sufficiently low level and making the longitudinal dimension thereof sufficiently large. Disadvantageously, however, since the LDD region constantly provides a parasitic resistance, such a configuration considerably limits the ON current of the thin film transistor. As another disadvantage thereof, since the effectual drain voltage becomes smaller, the second phenomenon pointed out above becomes more problematic.
Configuration C: As illustrated in FIG. 15A, two thin film transistors are connected in series. With such a serial connection, a certain level of voltage Vbias is applied to the gate of one of these thin film transistors that lies at the drain side. FIG. 15B illustrates, under such a configuration, the voltage-current characteristics of the source-side thin film transistor TFTs and those of the drain-side thin film transistor TFTd with a node voltage Vm taken as a parameter. In FIG. 15B, the broken lines represent the voltage-current characteristics of the drain-side TFTd when the drain voltage Vd is changed into Vd1, Vd2, Vd3, and Vd4, respectively. The intersection of the voltage-current characteristics of the source-side TFTs and those of the drain-side TFTd that is shown in FIG. 15B represents an operating current taken when two of these thin film transistors are connected in series. As illustrated in FIG. 15C, its saturated operations are remarkably enhanced. This is a popular technique used in MOS analog circuits that employ a so-called cascode connection. Disadvantageously, however, if the cascode configuration is adopted, it becomes necessary to provide a separate circuit that can generate Vbias. As still another disadvantage thereof, the input range of Vgate will be limit ed.
Configuration D: As illustrated in FIG. 16A, it is possible to offer advantageous operational effects that are similar to those achieved when the configuration C described above is adopted by connecting two thin film transistors in series and by electrically connecting the gate of one of these two thin film transistors with the gate of the other thereof, thereby integrating Vbias and Vgate into common one. FIG. 16B illustrates, under such a configuration, the voltage-current characteristics of the source-side TFTs and those of the drain-side TFTd with a node voltage Vm taken as a parameter. In FIG. 16B, the broken lines represent the voltage-current characteristics of the drain-side TFTd when the drain voltage Vd is changed into Vd1, Vd2, Vd3, and Vd4, respectively. The intersection of the voltage-current characteristics of the source-side TFTs and those of the drain-side TFTd that is shown in FIG. 16B represents an operating current taken when two of these thin film transistors are connected in series. As illustrated in FIG. 16C, its saturated operations are remarkably enhanced. Examples of the above-described configurations are disclosed n, for example, “L. Mariucci et al., AM-LCD '03 pp. 57-60” and “Woo-Jin Nam et al., IDW'04 pp. 307-310”.
In a case where the configuration D that is explained while making reference to FIG. 16 is adopted, it is clear that the operating point of TFTd is limited into the neighborhood of the pinch off voltage point Vp of TFTs. It is thus impossible to obtain expected advantageous operational effects if the operating point thereof falls within the linear operation range of TFTs. For this reason, in order to obtain a good operating point, for example, it is necessary to set a value calculated as the result of dividing the channel width Wd of TFTd by the channel length Ld thereof (Wd/Ld) several times as large as a value calculated as the result of dividing the channel width Ws of TFTs by the channel length Ls thereof (Ws/Ls). Disadvantageously, such a requirement significantly narrows the freedom of layout design.
As the voltage-current characteristics of a typical thin film transistor, the inclination of Ids relative to Vds tends to be large in the vicinity of the pinch off voltage point Vp. For this reason, in order to address the second problematic phenomenon described above, it is necessary to set a considerably large ratio that is computed as (Wd/Ld)/(Ws/Ls). Therefore, if the layout thereof is designed without going beyond an ordinary boundary of engineer's design discretion, gate capacitance increases to cause the degradation in the high frequency characteristics of the circuit operations thereof; and in addition thereto, the area occupancy of the thin film transistor increases disadvantageously.